图 书 馆
一种针对机器学习而基于现场可编程门阵列的映射归约框架FPGA-based MapReduce Framework for Machine Learning |
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| 课程网址: | http://videolectures.net/nipsworkshops09_xu_fpga/ |
| 主讲教师: | Ningyi Xu |
| 开课单位: | 微软公司 |
| 开课时间: | 2010-01-19 |
| 课程语种: | 英语 |
| 中文简介: |  |
| 课程简介: | Machine learning algorithms are becoming increasingly important in our daily life. However, training on very large scale datasets is usually very slow. FPGA is a reconfigurable platform that can achieve high parallelism and data throughput. Many works have been done on accelerating machine learning algorithms on FPGA. In this paper, we adapt Google's MapReduce model to FPGA by realizing an on-chip MapReduce framework for machine learning algorithms. A processor scheduler is implemented for the maximum computation resource utilization and load balancing. In accordance with the characteristics of many machine learning algorithms, a common data access scheme is carefully designed to maximize data throughput for large scale dataset. This framework hides the task control, synchronization and communication away from designers to shorten development cycles. In a case study of RankBoost acceleration, up to 31.8x speedup is achieved versus CPU-based design, which is comparable with a fully manually designed version. We also discuss the implementations of two other machine learning algorithms, SVM and PageRank, to demonstrate the capability of the framework. |
| 关 键 词: | 机器学习算法; 并行性; 数据吞吐量; 资源利用率; 处理器调度程序 |
| 课程来源: | 视频讲座网 |
| 最后编审: | 2020-06-15：wuyq |
| 阅读次数: | 32 |